Methods for Reducing Scratch Defects in Chemical Mechanical Planarization

ABSTRACT

Disclosed is a method of forming a semiconductor device. The method includes providing a precursor having a substrate and protrusions over the substrate. The protrusions are interposed by trenches. The method further includes depositing a first dielectric layer over the protrusions and filling the trenches. The first dielectric layer has a first hardness. The method further includes treating the first dielectric layer with an oxidizer. The method further includes performing a chemical mechanical planarization (CMP) process to the first dielectric layer.

PRIORITY DATA

This application is a continuation of U.S. patent application Ser. No.15/182,291, filed Jun. 14, 2016, which claims the benefit of U.S. Prov.App. No. 62/287,642 entitled “Methods for Reducing Scratch Defects inChemical Mechanical Planarization,” filed Jan. 27, 2016, each of whichis incorporated herein by reference in its entirety.

BACKGROUND

The semiconductor integrated circuit (IC) industry has experiencedexponential growth. Technological advances in IC materials and designhave produced generations of ICs where each generation has smaller andmore complex circuits than the previous generation. This scaling downprocess generally provides benefits by increasing production efficiencyand lowering associated costs. Such scaling down has also increased thecomplexity of processing and manufacturing ICs. For these technologicaladvancements to be realized, similar developments in IC processing andmanufacturing are needed.

For example, multi-gate devices have been introduced in an effort toimprove gate control by increasing gate-channel coupling, reduceOFF-state current, and reduce short-channel effects (SCEs). One type ofthe multi-gate devices is FinFETs—transistors with a fin-likesemiconductor channel (“fin”) and a gate electrode engaging the fin ontwo or three sides thereof. In a typical FinFET formation process, finsare formed out of a substrate (e.g., through epitaxial and/or etchingprocesses) and are separated by deep trenches. The trenches aresubsequently filled with a gap-fill dielectric material as an isolationstructure. As the device miniaturization continues, the aspect ratio(height vs. width) of the trenches also increases. As a result, thedensity of the gap-fill material is decreased in order to fill the deeptrenches properly. However, the low density gap-fill material frequentlysuffers from scratch defects during subsequent chemical mechanicalplanarization (CMP) processes. Furthermore, a single layer of thegap-fill material is sometimes inadequate to meet low wet etch raterequirements. In these cases, two or more layers of gap-fill materialsare deposited as a film stack. Adjacent films in the film stacksometimes suffer from poor adhesion between them.

Accordingly, improvements in these areas are desired.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the followingdetailed description when read with the accompanying figures. It isemphasized that, in accordance with the standard practice in theindustry, various features are not drawn to scale. In fact, thedimensions of the various features may be arbitrarily increased orreduced for clarity of discussion.

FIG. 1 is a flow chart of a method of forming a semiconductor deviceaccording to various aspects of the present disclosure.

FIGS. 2A, 2B, 2C, 2D, 2E, 2F, and 2G are cross-sectional views of aportion of a semiconductor device in various fabrication stagesaccording to the method in FIG. 1, in accordance to an embodiment.

FIG. 3 is a flow chart of an embodiment of the method in FIG. 1,according to various aspects of the present disclosure.

FIG. 4A is a perspective view of a portion of a semiconductor devicefabricated with the method in FIG. 3, in accordance to an embodiment.

FIGS. 4B, 4C, 4D, 4E, 4F, and 4G are cross-sectional views of a portionof the semiconductor device in FIG. 4A during various fabrication stagesaccording to embodiments of the method in FIG. 3.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, orexamples, for implementing different features of the provided subjectmatter. Specific examples of components and arrangements are describedbelow to simplify the present disclosure. These are, of course, merelyexamples and are not intended to be limiting. For example, the formationof a first feature over or on a second feature in the description thatfollows may include embodiments in which the first and second featuresare formed in direct contact, and may also include embodiments in whichadditional features may be formed between the first and second features,such that the first and second features may not be in direct contact. Inaddition, the present disclosure may repeat reference numerals and/orletters in the various examples. This repetition is for the purpose ofsimplicity and clarity and does not in itself dictate a relationshipbetween the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,”“above,” “upper” and the like, may be used herein for ease ofdescription to describe one element or feature's relationship to anotherelement(s) or feature(s) as illustrated in the figures. The spatiallyrelative terms are intended to encompass different orientations of thedevice in use or operation in addition to the orientation depicted inthe figures. The apparatus may be otherwise oriented (rotated 90 degreesor at other orientations) and the spatially relative descriptors usedherein may likewise be interpreted accordingly.

The present disclosure is generally related to methods for semiconductordevice fabrication, and more particularly to methods of forming FinFETsas well as replacement gate processes for FinFETs. In a typical FinFETprocess, multiple parallel fins are formed as protrusions over asubstrate and are separated by deep trenches. Then, a dielectricgap-fill material is deposited into the trenches and over the fins asisolation. As the process nodes are scaled down, an aspect ratio of thedeep trenches (a ratio between a height and a width of the deeptrenches) has increased. In some cases, the aspect ratio may be 12 orgreater. Consequently, it may be difficult to properly fill the deeptrenches with a dense gap-fill material. To counter this issue, amaterial having lower density is typically used as the gap-fill materialin advanced process nodes. However, such lower density materialfrequently suffers from defects (e.g., scratch defects) duringsubsequent CMP process. Such CMP defects may cause leakage, shorts,opens, or other problems in the final IC products. Another issue inFinFET formation is poor adhesion between two or more layers of gap-fillmaterials. Although a lower density gap-fill material can fill deeptrenches, its wet etch resistance may not be sufficient in some cases.Accordingly, a higher density gap-fill material is deposited over thelower density gap-fill material as a complement. The interface betweenthe higher density and the lower density gap-fill materials may sufferfrom poor adhesion.

The present disclosure provides methods for strengthening such lowerdensity gap-fill material before it undergoes the CMP process, therebyreducing CMP defects in the final IC products. Some embodiments of thepresent disclosure strengthen the lower density gap-fill material bytreating a top portion of the material in a thermally controlled aqueousoxidizer. Such methods can be readily integrated into existingmanufacturing flow. Furthermore, the treated portion of the material hasgood adhesion with a higher density gap-fill material deposited thereon.

Embodiments of the present disclosure may be applied in replacement gateprocesses in addition to fin formation processes. One of ordinary skillmay recognize other examples of semiconductor devices and manufacturingflows that may benefit from aspects of the present disclosure.

FIG. 1 shows a flow chart of a method 10 of forming a semiconductordevice 100 having FinFETs, according to various aspects of the presentdisclosure. FIG. 3 shows a flow chart of a method 50 of forming asemiconductor device 200 using a replacement gate process, according tovarious aspects of the present disclosure. The method 50 may beconsidered an embodiment of the method 10. The methods 10 and 50 aremerely examples, and are not intended to limit the present disclosurebeyond what is explicitly recited in the claims. Additional operationscan be provided before, during, and after the methods 10 and 50, andsome operations described can be replaced, eliminated, or relocated foradditional embodiments of the methods. The method 10 is described belowin conjunction with FIGS. 2A-2G, while the method 50 is described belowin conjunction with FIGS. 4A-4G.

As will be seen, each of the semiconductor devices 100 and 200 may beincluded in an IC such as a microprocessor, memory device, and/or otherIC which may comprise passive components such as resistors, capacitors,and inductors, and active components such as p-type field effecttransistors (PFET), n-type FET (NFET), metal-oxide semiconductor fieldeffect transistors (MOSFET), complementary metal-oxide semiconductor(CMOS) transistors, bipolar transistors, high voltage transistors, highfrequency transistors, multi-gate FETs including FinFETs, andcombinations thereof.

Referring to FIG. 1, at operation 12, the method 10 provides (or isprovided with) a precursor of the device 100. For the convenience ofdiscussion, the precursor is also referred to as the device 100.Referring to FIG. 2A, the device 100 includes a substrate 102 andmultiple protrusions 104 over the substrate 102. The protrusions 104 areseparated (or interposed) by trenches 110. In embodiments, the substrate102 may be a semiconductor substrate such as a silicon wafer. Thesubstrate 102 may also include other semiconductors such as germanium, acompound semiconductor such as silicon carbide, gallium arsenide,gallium phosphide, indium phosphide, indium arsenide, and/or indiumantimonide, an alloy semiconductor such as GaAsP, AlInAs, AlGaAs,InGaAs, GaInP, and/or GaInAsP, or combinations thereof. Further, thesubstrate 102 may optionally include epitaxial layers, be strained forperformance enhancement, include a silicon-on-insulator structure,and/or have other suitable enhancement features.

In the present embodiment, the protrusions 104 include semiconductorfins 106 and a dielectric hard mask (HM) layer 108. The semiconductorfins 106 may be formed out of portions of the substrate 102. Thedielectric HM layer 108 may include silicon nitride or other suitablematerial(s). In an embodiment, the protrusions 104 are formed by one ormore photolithography processes and etching processes. In an exemplaryprocess, the dielectric HM layer 108 is deposited as a blanket layerover the substrate 102 by chemical vapor deposition (CVD), plasmaenhanced CVD (PECVD), physical vapor deposition (PVD), thermaloxidation, or other techniques. Then, a masking element is formed overthe dielectric HM layer 108 using a photolithography process. Thephotolithography process may include forming a photoresist (or resist)over the blanket HM layer 108, exposing the resist to a pattern thatdefines geometrical shapes for the fins 106 (or the trenches 110),performing post-exposure bake processes, and developing the resist toform the masking element. The masking element provides openingscorresponding to the trenches 110.

Subsequently, the blanket HM layer 108 and the substrate 102 are etchedthrough the openings to form the protrusions 104 as shown in FIG. 2A,using a dry etching process, a wet etching process, or other suitableetching techniques. For example, a dry etching process may implement anoxygen-containing gas, a fluorine-containing gas (e.g., CF₄, SF₆, CH₂F₂,CHF₃, and/or C₂F₆), a chlorine-containing gas (e.g., Cl₂, CHCl₃, CCl₄,and/or BCl₃), a bromine-containing gas (e.g., HBr and/or CHBR₃), aniodine-containing gas, other suitable gases and/or plasmas, and/orcombinations thereof. For example, a wet etching process may compriseetching in diluted hydrofluoric acid (DHF); potassium hydroxide (KOH)solution; ammonia; a solution containing hydrofluoric acid (HF), nitricacid (HNO₃), and/or acetic acid (CH₃COOH); or other suitable wetetchant.

As shown in FIG. 2A, the protrusions 104 provide a top surface S₁₀₄. Thetrenches 110 each have a width W₁₁₀ in the “X” direction and a heightH₁₁₀ in the “Z” direction. An aspect ratio of the trenches 110 isdefined to be a ratio of H₁₁₀ over W₁₁₀. The aspect ratio increases asthe device miniaturization continues. In an embodiment, the aspect ratiois 12 or greater.

At operation 14, the method 10 (FIG. 1) deposits a dielectric layer 114over the protrusions 104 and filling the trenches 110. Referring to FIG.2B, the dielectric layer 114 buries the protrusions 104 underneath andelectrically isolates the protrusions 104 from one another. In thepresent embodiment, before the dielectric layer 114 is deposited, aliner layer 112 is formed over surfaces of the protrusions 104. Theliner layer 112 includes silicon oxide in one example and may be formedby thermal oxidation, CVD, PVD, or other deposition techniques. Theliner layer 112 may comprise other dielectric material(s), and may beomitted in some embodiments.

In the present embodiment, in order to properly fill the topography overthe substrate 102 and particularly due to the high aspect ratio of thetrenches 110, a low density dielectric material containing silicon andoxygen is used as the dielectric layer 114. Furthermore, the operation14 uses a flowable CVD (FCVD) method to deposit the dielectric layer114. For example, the operation 14 may introduce a silicon-containingcompound and an oxygen-containing compound as deposition precursors. Thesilicon-containing compound and the oxygen-containing compound react toform a flowable dielectric material (such as a liquid compound), therebyfilling the trenches 110. In alternative embodiments, the dielectriclayer 114 may be deposited using other CVD methods or other depositiontechniques such as spin coating. In embodiments, materials suitable forthe dielectric layer 114 include tetraethylorthosilicate oxide, un-dopedsilicate glass (USG), or doped silicon oxide such as fused silica glass(FSG), phosphosilicate glass (PSG), boron doped silicon glass,borophosphosilicate glass (BPSG), other silicon- and oxygen-containinglow density dielectric materials, and other suitable dielectricmaterials. A subsequent annealing process is performed to convert theflowable dielectric material to a solid material. For example, theannealing process may be performed at a temperature of about 300 degreesCelsius (° C.) to 1200° C. for a period of about two to ten hours.However, annealing the device 100 at a high temperature for a prolongedperiod is not desirable in some instances. For example, such annealingprocess may eliminate tensile strains in n-channel devices and degradedevice performance. This problem is generally referred to as strainrelaxation. Furthermore, even with the annealing process, the dielectriclayer 114 still may not have enough wet etch resistance for subsequentfabrication steps.

In one particular example, a subsequent fabrication step includes achemical mechanical planarization (CMP) process to the dielectric layer114. The CMP process is intended to planarize a top surface of thedevice 100 and to expose the protrusions 104. Due to the relatively lowmaterial density in the dielectric layer 114, the CMP process mightcause various defects in the dielectric layer 114 in some instances. TheCMP defects may include organic residues, water marks, particleadherence and impingement, corrosion pit, and scratches. CMP scratchdefects are particularly serious because they may cause short circuits,open circuits, and/or pattern removal in large areas, thereby affectingyield and long term reliability of the IC devices. The inventors of thepresent disclosure have discovered an efficient and effective way ofstrengthening the dielectric layer 114, thereby reducing CMP scratchdefects in subsequent fabrication.

At operation 16, the method 10 (FIG. 1) treats the dielectric layer 114with an oxidizer 116. Referring to FIG. 2C, in an embodiment, theoxidizer 116 is applied evenly across an entire surface of the device100. In the present embodiment, the oxidizer 116 is an aqueous oxidizer,which makes the operation 16 readily integrable with other fabricationsteps of the method 10, such as the operation 14 and operation 18 to bediscussed later. For example, the operations 14, 16, and 18 may all beperformed in a wet bench manufacturing environment. In an embodiment,the aqueous oxidizer 116 is deionized water (DIW). In anotherembodiment, the aqueous oxidizer 116 is dilute hydrofluoric acid (DHF).Since DHF may have both etching and oxidizing effects upon thedielectric layer 114 (e.g., silicon oxide), the concentration ofhydrofluoric acid (HF) in the DHF oxidizer 116 is tuned such that theDHF oxidizer 116 properly oxidizes the dielectric layer 114 withoutcausing too much film loss at the same time. In an embodiment, theconcentration of HF in the DHF oxidizer 116 is tuned to be in a rangefrom 0.005% to 0.1%. The aqueous oxidizer 116 may be applied onto thedielectric layer 114 using spray, spin-on, or other suitable techniques.In an embodiment, the operation 16 may apply more than one oxidizer in asequential manner. For example, the operation 16 may apply DIW (or DHF)as a first oxidizer. After some treatment time, the operation 16 appliesDHF (or DIW) as a second oxidizer that is different from the firstoxidizer. Compared with the annealing step in the operation 14, theoperation 16 is more efficient in oxidation. Even though the annealingstep may use wet annealing with water steam (or water vapor), the watercontents are rather diluted due to the use of carrier gas, such asnitrogen gas, in the annealing step.

In the present embodiment, the operation 16 is performed in athermally-controlled manner. Particularly, the operation 16 is performedat a temperature below 100° C., which is consistent with certain wetbench manufacturing flows when the oxidizer 116 is aqueous. For example,the operation 16 may be performed at a temperature ranging from 15° C.to 90° C., such as at room temperature of about 25° C. Notably, suchtemperature is much lower than typical temperatures used for annealingthe dielectric layer 114 in the operation 14. Accordingly, the operation16 does not lead to the strain relaxation issue discussed above. Invarious embodiments, the operation 16 may be performed for few secondsto few minutes, such as from 3 seconds to about 120 seconds, dependingon the oxidizer used and the treatment temperature.

In alternative embodiments, the oxidizer 116 may be other aqueoussolutions in addition to DIW and DHF. For example, the oxidizer 116 maybe dilute hydrogen peroxide (H₂O₂). In further embodiments, the oxidizer116 may be a gaseous oxidizer, such as oxygen gas.

FIG. 2D illustrates the device 100 after the operation 16 is completed.Referring to FIG. 2D, an upper portion 114A of the dielectric layer 114is treated with the oxidizer 116, and a lower portion 114B of thedielectric layer 114 is not treated or is insignificantly treated. Theupper portion 114A (also referred to as the treated portion 114A) has ahigher hardness than the lower portion 114B (also referred to as theuntreated portion 114B). In some embodiments, the hardness of thetreated portion 114A is about 1.1˜1.2 times higher than the hardness ofthe untreated portion 114B. Additionally, the treated portion 114A mayhave a higher film density than the untreated portion 114B. An imaginaryboundary between the portions 114A and 114B is denoted as S_(114A). Inreality, the hardness (as well as film density) of the dielectric layer114 may change gradually from its top surface towards the substrate 102.Therefore, there is no abrupt change of material at the boundaryS_(114A). In an example where the dielectric layer 114 contains siliconand oxygen, the treated portion 114A now has higher contents ofsilicon-oxygen bonds than the untreated portion 114B. In the presentembodiment, the temperature, oxidizer concentration, and treatment timeof the operation 16 are tuned such that the boundary S_(114A) is belowthe top surface S₁₀₄ of the protrusions 104. The treated portion 114Aprovides sufficient film hardness for reducing CMP scratch defectsthereupon.

At operation 18, the method 10 (FIG. 1) deposits another dielectriclayer 118 over the treated portion 114A (FIG. 2E). The dielectric layer118 has a higher hardness than the dielectric layer 114 before it istreated in the operation 16. For example, the hardness of the dielectriclayer 118 may be 1.1 to 1.5 times higher than that of the dielectriclayer 114 before it is treated. This is to satisfy the needs of bothfilm thickness and low etch resistance for a subsequent CMP process. Inan embodiment, the hardness of the dielectric layer 118 is even higherthan the treated portion 114A. Notably, adhesion between the treatedportion 114A and the dielectric layer 118 is better than what would bebetween the original dielectric layer 114 and the dielectric layer 118.

In embodiments, materials suitable for the dielectric layer 118 includetetraethylorthosilicate oxide, un-doped silicate glass (USG), or dopedsilicon oxide such as fused silica glass (FSG), phosphosilicate glass(PSG), boron doped silicon glass, borophosphosilicate glass (BPSG),other silicon and oxygen containing dielectric materials, and othersuitable dielectric materials. In an embodiment, the dielectric layer118 is deposited using an FCVD method. Alternatively, the dielectriclayer 118 may be deposited using other CVD methods, PVD, spin coating,or other deposition techniques.

At operation 20, the method 10 (FIG. 1) performs a CMP process 120 torecess the dielectric layers 118 and 114 (FIG. 2F). The CMP process 120uses appropriate CMP consumables such as CMP polishing pad, CMP slurry,and CMP conditioner tuned for recessing the materials of the dielectriclayers 118 and 114. For example, the CMP polishing pad may be a hard pador a soft pad, and may further have pores or grooves. The CMP slurry mayinclude ferric nitrate, peroxide, potassium iodate, ammonia, silica,alumina, and/or other slurry materials. The CMP slurry may furthercontain abrasives, pH adjustors, and one or more additives such asoxidizing agents, complexing agents, corrosion inhibitors, anddispersion agents. In an embodiment, the dielectric layers 118 and 114contain silicon oxide, and the CMP process 120 uses cerium oxide (CeO₂)based slurry. The CMP process 120 completely removes the dielectriclayer 118 and partially removes the dielectric layer 114, therebyexposing topography underneath for subsequent fabrication (FIG. 2G). Inan embodiment, the CMP process 120 includes first and second stages. Inthe first stage, a higher down-force is applied for completely removingthe dielectric layer 118 and partially removing the dielectric layer114. In the second stage, a lower down-force is applied for precisethickness control in the remaining portion of the dielectric layer 114.Due to the oxidation treatment, CMP scratch defects at the dielectriclayer 114 are significantly reduced. At some instances, a reduction ofCMP scratch defects by 50% to 75% has been observed.

At operation 22, the method 10 (FIG. 1) performs further steps tocomplete a final FinFET device. In one example, the operation 22replaces the semiconductor fins 106 with one or more epitaxially grownsemiconductor layers. To further this example, the operation 22 removesthe dielectric HM layer 108 and partially removes the semiconductor fins106 by one or more etching processes, thereby forming openings.Subsequently, the operation 22 epitaxially grows semiconductor layers inthe openings. In another example, the operation 22 recesses thedielectric layer 114 to partially expose the semiconductor fins 106.Subsequently, the operation 22 forms gate electrodes over thesemiconductor fins 106, forms source and drain features, forms contacts,and so on, in order to form a FinFET.

FIG. 3 shows a flow chart of the method 50 of forming the semiconductordevice 200 using a replacement gate process, according to variousaspects of the present disclosure. The method 50 may be considered anembodiment of the method 10. The method 50 is briefly discussed below,in conjunction with FIGS. 4A-4G. FIG. 4A is a perspective view of aportion of the semiconductor device 200, while FIGS. 4B-4G arecross-sectional view of the portion of the semiconductor device 200along the “1-1” line in FIG. 4A.

At operation 12A, the method 50 (FIG. 3) provides (or is provided with)a precursor having a substrate 202 and protrusions 208 over thesubstrate 202. Referring to FIG. 4A, the protrusions 208 are dummy gatestructures for a replacement gate process. Hence, they are also referredto as the dummy gates 208 in the following discussion. The dummy gates208 are separated by trenches 230. The device 200 further includes fins204 over the substrate 202 and an isolation structure 206 over thesubstrate 202 and between adjacent fins 204. In an embodiment, thesubstrate 202, the fins 204, and the isolation structure 206 may besimilar to the substrate 102, the fins 106, and the dielectric layer 114in FIG. 2G, respectively. For the purposes of simplicity, detaileddescriptions of these features are omitted.

Referring to FIG. 4B, the dummy gates 208 each include an oxide layer222, a gate electrode layer 224, a hard mask layer 226, and a cappinglayer 228. The oxide layer 222 may comprise a dielectric material suchas silicon oxide. The gate electrode layer 224 may comprise a singlelayer or multilayer structure. In an embodiment, the gate electrodelayer 224 comprises polysilicon. In an embodiment, the hard mask layer226 comprises silicon nitride and the capping layer 228 comprisessilicon oxide. Each of the layers 222, 224, 226, and 228 may be formedby chemical oxidation, thermal oxidation, atomic layer deposition (ALD),CVD, lower pressure CVD, PECVD, and/or other suitable methods. In someembodiments, the dummy gates 208 are surrounded by gate spacers (notshown). The dummy gates 208 engage channel regions 212 of the underlyingfins 204. In the present embodiment, the two dummy gates 208 share asource/drain (S/D) region 210. In alternative embodiments, the two dummygates 208 do not share an S/D region 210. The trenches 230 have a widthW₂₃₀ along the “Y” direction (FinFET channel length direction) and aheight H₂₃₀ along the “Z” direction. In embodiments, an aspect ratio ofthe trenches 230 (as a ratio of H₂₃₀ over W₂₃₀) may be large.

At operation 14A, the method 50 (FIG. 3) deposits a dielectric layer 234over the dummy gates 208 and filling the trenches 230. Referring to FIG.4C, in the present embodiment, an etch stop layer (ESL) 232 is formedover the fins 204 and the dummy gates 208 before the dielectric layer234 is deposited. The ESL 232 may include SiN, SiCN, SiCON, or othersuitable materials and may be formed by CVD, PVD, ALD, or other suitablemethods. In the present embodiment, the dielectric layer 234 uses a lowdensity dielectric material containing silicon and oxygen in order toproperly fill the trenches 230. Further, the dielectric layer 234 isdeposited using an FCVD method. The materials used for the dielectriclayer 234 and the method of deposition thereof are similar to what isdiscussed with respect to the dielectric layer 114 in the operation 14(FIG. 1). In some instances, the hardness of the dielectric layer 234may not satisfy subsequent fabrication steps. In the present embodiment,the dielectric layer 234 is treated with an oxidizer to increase itshardness, as discussed below.

At operation 16, the method 50 (FIG. 3) treats the dielectric layer 234with an oxidizer 236. Many respects of the oxidizer 236 aresubstantially the same as those of the oxidizer 116. Accordingly, somedetails of the oxidizer 236 are omitted here for the purpose ofsimplicity. In embodiments, the oxidizer 236 is an aqueous oxidizer suchas DIW and DHF. The operation 16 is performed in a thermally controlledmanner. Particularly, it is performed at a temperature below 100° C.,such as in a range from 15° C. to 90° C. As a result, an upper portion234A (or treated portion 234A) of the dielectric layer 234 is oxidizedto have a higher hardness than a lower portion 234B (or untreatedportion 234B) of the dielectric layer 234 which is not oxidized orinsignificantly oxidized (FIG. 4D). In some embodiments, the hardness ofthe treated portion 234A is about 1.1˜1.2 times higher than the hardnessof the untreated portion 234B. Additionally, the upper portion 234A mayhave a higher film density than the lower portion 234B. In the presentembodiment, the upper portion 234A extends below a top surface of thedummy gates 208.

At operation 18, the method 50 (FIG. 3) deposits another dielectriclayer 238 over the treated portion 234A. The dielectric layer 238 hashardness higher than that of the dielectric layer 234 before it istreated. For example, the hardness of the dielectric layer 238 may be1.1 to 1.5 times higher than that of the dielectric layer 234 before itis treated. The material(s) used for the dielectric layer 238 and themethods of deposition thereof are similar to what is discussed withrespect to the dielectric layer 118 (FIG. 2E). Due to the treatment,adhesion between the dielectric layers 234 and 238 is improved.

At operation 20, the method 50 (FIG. 3) performs a CMP process 240 torecess the dielectric layers 238 and 234 (FIG. 4F). Many respects of theCMP process 240 may be substantially the same as those of the CMPprocess 120 (FIG. 2F). Due to the treatment in the operation 16, thedielectric layer 234 (particularly the treated portion 234A) helpsreduce scratch defects during the CMP process 240.

At operation 22A, the method 50 (FIG. 3) performs further steps tocomplete a final FinFET device. In the present embodiment, the operation22A performs various etching, deposition, and planarization processes toreplace the dummy gates 208 with a final gate 242 (FIG. 4G). Forexample, the operation 22A may remove the layers 228, 226, 224, and 222by one or more etching processes, thereby forming openings.Subsequently, the operation 22 deposits the final gate 242 in theopening and performs a CMP process to planarize a top surface of thedevice 200. The final gate 242 may include an interfacial layer, a gatedielectric layer such as a high-k gate dielectric layer, a work functionmetal layer, and a metal fill layer. The various layers of the finalgate 242 may be formed by chemical oxidation, thermal oxidation, ALD,CVD, plating, and/or other suitable methods.

Although not intended to be limiting, one or more embodiments of thepresent disclosure provide many benefits to a semiconductor device and aformation process thereof. For example, embodiments of the presentdisclosure provide methods for strengthening a dielectric layer, therebyreducing scratch defects in subsequent CMP processes. The strengtheneddielectric layer also provides better adhesion with another dielectriclayer deposited thereon. Methods according to embodiments of the presentdisclosure are cost-effective because they may be performed at arelatively low temperature (e.g., under 100° C.) with readily availableoxidizing solutions. Yet, they may achieve a significant reduction inCMP scratch defects. In addition, methods according to embodiments ofthe present disclosure can be readily integrated with existingmanufacturing flow.

In one exemplary aspect, the present disclosure is directed to a methodof forming a semiconductor device. The method includes providing aprecursor having a substrate and protrusions over the substrate. Theprotrusions are interposed by trenches. The method further includesdepositing a first dielectric layer over the protrusions and filling thetrenches, the first dielectric layer having a first hardness. The methodfurther includes treating the first dielectric layer with an oxidizerand performing a chemical mechanical planarization (CMP) process to thefirst dielectric layer.

In another exemplary aspect, the present disclosure is directed to amethod of forming a semiconductor device. The method includes providinga precursor having a substrate and fins over the substrate, the finsbeing interposed by trenches. The method further includes depositing afirst silicon oxide layer over the fins and filling the trenches, thefirst silicon oxide layer having a first hardness. The method furtherincludes treating the first silicon oxide layer with an aqueousoxidizer, resulting in a treated portion of the first silicon oxidelayer above an untreated portion of the first silicon oxide layer. Thetreated portion of the first silicon oxide layer has a second hardnessgreater than the first hardness. The method further includes depositinga second silicon oxide layer over the treated portion of the firstsilicon oxide layer, wherein the second silicon oxide layer has a thirdhardness higher than the first hardness. The method further includesperforming a chemical mechanical planarization (CMP) process to thesecond and first silicon oxide layers.

In yet another exemplary aspect, the present disclosure is directed to amethod of forming a semiconductor device. The method includes providinga precursor having a substrate and protrusions over the substrate. Theprotrusions are interposed by trenches. The method further includesdepositing a first silicon oxide layer over the protrusions and fillingthe trenches. The first silicon oxide layer has a first hardness. Themethod further includes treating the first silicon oxide layer with anaqueous oxidizer at a temperature lower than 100 degrees Celsius (° C.),resulting in a treated portion of the first silicon oxide layer, whereinthe treated portion has a second hardness greater than the firsthardness. The method further includes depositing a second silicon oxidelayer over the treated portion, wherein the second silicon oxide layerhas a third hardness higher than the first hardness. The method furtherincludes performing a chemical mechanical planarization (CMP) process tothe second and first silicon oxide layers.

The foregoing outlines features of several embodiments so that those ofordinary skill in the art may better understand the aspects of thepresent disclosure. Those of ordinary skill in the art should appreciatethat they may readily use the present disclosure as a basis fordesigning or modifying other processes and structures for carrying outthe same purposes and/or achieving the same advantages of theembodiments introduced herein. Those of ordinary skill in the art shouldalso realize that such equivalent constructions do not depart from thespirit and scope of the present disclosure, and that they may makevarious changes, substitutions, and alterations herein without departingfrom the spirit and scope of the present disclosure.

What is claimed is:
 1. A method of forming a semiconductor device, the method comprising: providing a substrate and fins over the substrate, the fins being interposed by trenches; depositing a first dielectric layer over the fins and filling the trenches, the first dielectric layer having a first hardness; hardening the first dielectric layer, resulting in a hardened portion of the first dielectric layer; after the hardening of the first dielectric layer, depositing a second dielectric layer over the hardened portion of the first dielectric layer, wherein the second dielectric layer has a second hardness higher than the first hardness; and performing a chemical mechanical planarization (CMP) process to both the first dielectric layer and the second dielectric layer to completely remove the second dielectric layer and partially remove the hardened portion of the first dielectric layer.
 2. The method of claim 1, wherein the hardening of the first dielectric layer comprises treating the first dielectric layer with an oxidizer.
 3. The method of claim 2, wherein the treating of the first dielectric layer is performed at a temperature ranging from 15° C. to 90° C. and the oxidizer is dilute hydrofluoric acid (DHF) and a concentration of hydrofluoric acid in the oxidizer ranges from 0.005% to 0.1%.
 4. The method of claim 2, wherein the treating of the first dielectric layer is performed at room temperature.
 5. The method of claim 2, wherein the oxidizer is aqueous.
 6. The method of claim 2, wherein the hardening of the first dielectric layer further comprises, after the treating of the first dielectric layer, treating the first dielectric layer with deionized water (DIW).
 7. The method of claim 1, wherein the hardened portion of the first dielectric layer extends below a top surface of the semiconductor fins.
 8. The method of claim 1, wherein an aspect ratio between a height and a width of the trenches is greater than
 12. 9. The method of claim 1, wherein the first and second dielectric layers include silicon and oxygen.
 10. A method of forming a semiconductor device, the method comprising: providing a substrate and semiconductor fins over the substrate, the semiconductor fins being interposed by trenches; depositing a first dielectric layer over the semiconductor fins and filling the trenches, the first dielectric layer containing silicon and oxygen and having a first content of silicon-oxygen bonds; treating the first dielectric layer with an aqueous oxidizer, resulting in a treated portion of the first dielectric layer above an untreated portion of the first dielectric layer, the treated portion of the first dielectric layer having a second content of silicon-oxygen bonds greater than the first content of silicon-oxygen bonds; depositing a second dielectric layer over the treated portion of the first dielectric layer; and performing a chemical mechanical planarization (CMP) process to completely remove the second dielectric layer and partially remove the treated portion of the first dielectric layer.
 11. The method of claim 10, wherein the aqueous oxidizer is deionized water (DIW).
 12. The method of claim 10, wherein the aqueous oxidizer is dilute hydrofluoric acid (DHF).
 13. The method of claim 12, wherein a concentration of hydrofluoric acid in the aqueous oxidizer ranges from 0.005% to 0.1%.
 14. A method of forming a semiconductor device, the method comprising: providing a substrate and dummy gate structures over the substrate, the dummy gate structures being interposed by trenches; depositing a first dielectric layer over the dummy gate structures and filling the trenches, the first dielectric layer containing silicon and oxygen; hardening the first dielectric layer with an aqueous oxidizer, resulting in a hardened portion of the first dielectric layer; depositing a second dielectric layer over the hardened portion; and performing a chemical mechanical planarization (CMP) process to completely remove the second dielectric layer and partially remove the hardened portion of the first dielectric layer.
 15. The method of claim 14, wherein the aqueous oxidizer is one of: deionized water (DIW) and dilute hydrofluoric acid (DHF).
 16. The method of claim 14, wherein the first dielectric layer has a first hardness before the hardening of the first dielectric layer, the hardened portion has a second hardness greater than the first hardness, and the second dielectric layer has a third hardness greater than the second hardness.
 17. The method of claim 14, wherein the hardening the first dielectric layer with an aqueous oxidizer comprises a first treating process with deionized water (DIW) and a second treating process with dilute hydrofluoric acid (DHF).
 18. The method of claim 17, wherein a concentration of hydrofluoric acid in the DHF ranges from 0.005% to 0.1%.
 19. The method of claim 14, further comprising annealing the first dielectric layer at a temperature between about 300° C. and about 1200° C.
 20. The method of claim 14, wherein each of the dummy gate structures comprises an oxide layer, a gate electrode layer over the oxide layer, and a hard mask layer over the gate electrode layer. 